The voltage amplification characteristics of a gated diode are known to be desirable in the design of high performance and low voltage memory circuits. Area-efficient implementations of gated diode structures, however, have remained elusive, primarily because planar gated diode structures are generally required to be significantly large in order to achieve sufficient capacitance. Typically, the “on” capacitance of a gated diode, which may be defined as the capacitance associated with the device when it is forward biased, must be about five to ten times that of the total load capacitance connected to the gated diode. This requires a gate area of the diode to be about a few times that of a load transistor used in conjunction with the gated diode, which, especially in a densely packed circuit application (e.g., a memory cell), can result in significantly increased cost.
Two simple implementations of a gated diode structure are shown in FIG. 1, wherein the capacitance characteristics of the gated diode are based on a standard metal-oxide-semiconductor field-effect transistor (MOSFET) structure 100 having two source/drain regions 102, or on an MOS structure 150 having a single source/drain region. When a gate 104 of either of the MOS structures 100, 150 is biased below inversion, there will be a very small capacitance between first and second terminals (terminal 1 and terminal 2) of the structure. Inversion in a MOS device is typically defined as a change in carrier type obtained by the application of an external voltage to the device. Inversion creates free carriers which cause the drain current in the MOS device. The small capacitance associated with a device biased below inversion consists primarily of parasitic capacitances, such as, for example, overlap capacitance between an edge of the gate 104 and a given source/drain region 102 of the MOS device. When the gate 104 is biased above inversion, a large capacitance (e.g., gate oxide inversion capacitance) is seen between the two terminals of the gated diode, due primarily to the formation of an inversion layer along a channel 106 in the MOS structure 100, 150.
The total capacitance associated with the MOS structure depends primarily on the planar layout area, which is, for large gated diodes, dominated by a gate-over-active area. In order to increase the capacitance, either a width (W) or a length (L) of the gate 104 in the gated diode must be increased. Increasing the length is preferred since the inversion capacitance increases while the overlap capacitance remains substantially unchanged. The length of the gated diode is limited, however, by a transit time required for a carrier to travel from the source/drain region 102 to a middle of the channel 106 (usually several hundred nanometers (nm), depending on the design).
The MOS structure may either contain both source and drain contacts tied together to form the second terminal of the gated diode, as in the case of MOSFET structure 100, or just one of the two contacts, as in the case of MOS structure 150. Using both source and drain contacts reduces carrier transit time by a factor of two, which may be important in certain high-speed applications. Using symmetric contacts also makes the capacitance of the MOSFET structure more insensitive to overlay errors, as the layout is symmetric between the source and drain. However, such a design undesirably requires a larger layout area and doubles the overlap capacitance.
Accordingly, there is a need for an improved gated diode structure, and techniques for the formation thereof, that does not suffer from one or more of the problems exhibited by conventional gated diode structures.